DIY bitcoin miner for Avalon A3255-Q48 chips – Pagina 1

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DIY bitcoin miner for Avalon A3255-Q48 chips - Page 1

How much did you pay for them?

I’d say just attempt and sell what you’ve got!

Unluckily for you, you are facing the dual hurdles of time lost ter vormgeving spil you’ve mentioned, and also the costs of local power. With energiewende I don’t think your situation will improve te the near future unless you can steal power from your neighbours .

I’d love to see what the final vormgeving looks like, I’ve always bot interested te buying the chips individually and putting a miner together. Please do postbode it if you get it finished

For the final PCB I will substitute it with a smaller (and cheaper) Lattice MachXO2 FPGA, and a Raspberry Pi will communicate with it overheen the serial port instead of a PC.

I already built a mining system with FPGA houtvezelplaat DE0-nano and Raspberry Pi spil

host just for joy. It is running stable for a month with ca. 10MH/s.

I found this tread while searching for purchasing the avalon chips to make my own avalon houtvezelplaat.

So i’m very interested te your project and would like to work with you to develop such a mining

system. I cannot program FPGAs but i can build a hardware proffessionally (with altium).

Maybe wij can help each other.

Yes, he does, it has a slightly different meaning te the Bitcoin world than te more general crypto, AFAIK, but it is an established term of kunst te the latter world. Does rather make a Brit blink at very first, however!

Hi, I’m also developing system based on A3255-Q48, with 32 chips vanaf houtvezelplaat, from scrape schematics, with objective of maximum spectacle, thus using individual config for each chip (to set max. clock for each chip), and using separate power supply for each chip and Altera FPGA (Cyclone-II) controller ter PQFP package, since my practice with BGA soldering quality is not too positive. Using FTDI 245R for USB I/O, and designed for ATX-24 power supply connector, with fan control circuits and temperature sensor included, mini-ITX formfactor.

Vanaf datasheet, words are:

So, of Legitimate words you observed, wij have only 8 (!) documented to some extent, and Ten words are unknown (assuming that Eighteen words that go through do not include the nonce word)

so, there they have 20 words! And, supposedly that worked after all, but I’m not fairly certain it’s the same chip – A3255, seems it’s the earlier one.

It shows this output:

Spil you can see, there are the midstate words (the getwork-data is ter little endian, so the last midstate word 0x3365f562 are encoded spil 62f56533 ter the midstate array).

and testing it for all nNonce, so that the resulting hash has a high number of leading zeros, better than specified ter the ",target",. SHA256 hashes the input te 512 bit chunks = 64 bytes. For the very first chunk that would be Four bytes for the version, 32 bytes for hashPrevBlcok and 28 bytes of hashMerkleRoot. This chunk doesn’t switch, which is the reason you have to calculate it only once for testing all nNonce values. The SHA256 state for this chunk is called ",midstate",.

maybe it is possible to port the mining vormgeving from DE0-nano to the avalon chips.

That can do someone who is familiar with VHDL vormgeving – i don’t know about how

ordinary or difficult it is to port.

host just for joy. It is running stable for a month with ca. 10MH/s.

I followed this guide for FPGA mining (open source) on DE0-nano and it works.

I inserted a correction into this guide to run it with RPi and a mining pool such a BTCguild.

Just notice the comment from sparkerdesign (its mij) to make it run with RPi.

at least size of gegevens is clear now (Trio words) and midstate confirmed at 8 words.

Related movie: My Top Five Indicators te Trading Crypto – The Instruments I use

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